I realized that the timer CPLD verilog was overly complicated. So I simplified it:

 1 // This CPLD is a timer circuit that generates a 500Hz tick. It takes a 2MHz
 2 // clock in. Scales that down to 125MHz with a 4 bit counter.
 3 // Then it counts 125 of those in a 7 bit counter that resets on 7c.
 4 // When the reset occurs, the pin_nINT line goes from Hi-Z to low.
 5 //
 6 // The falling edge of pin_nCS pin brings pin_nINT back to Hi-Z.
 7 //
 8 // SCK and Dout are used to read the 3 bit tick counter. This is used
 9 // to ensure that the count is kept synched. Dout is updated on the
10 // falling edge of SCK and the MSB is shifted first. 
11 //
12 
13 
14 module timer (
15     input pin_CLK,
16     input pin_nCS,
17     input pin_SCK,
18     output pin_Dout,
19     output pin_nINT
20     );
21 
22     reg [10:0] counter;
23     reg [2:0] ticks;
24     reg [2:0] tickShift;
25     wire nTick;
26     reg nInt;
27     reg nCS0;
28     reg nCS1;
29     reg SCK0;
30 
31     // Not synthesized. Just for testing
32     initial begin
33         counter = 0;
34         ticks = 0;
35     end
36 
37     assign nTick = ~(counter == 11'b11111001111); // 124'15 causes 125'0->0'0
38     assign pin_nINT = (nInt == 1'b1) ? 1'bz : 1'b0;
39     assign pin_Dout = pin_nCS ? 1'bz : tickShift[2];
40 
41     always @(posedge pin_CLK) begin
42         if (nTick == 1'b0) begin
43             counter <= 0;
44             ticks <= ticks+1;
45         end
46         else begin
47             counter <= counter+1;
48         end
49 
50         nCS0 <= pin_nCS;
51         nCS1 <= nCS0;
52 
53         // Set interrupt on the CLK. Reset it on the falling edge of
54         // pin_nCS+2 clocks
55         if (nTick == 1'b0) begin
56             nInt <= 1'b0; 
57         end
58         else if ((nCS1 & (~nCS0)) == 1'b1) begin
59             nInt <= 1'b1; 
60         end
61 
62         // search for falling edge of SCK in CLK
63         SCK0 <= pin_SCK;
64         if (~pin_nCS) begin
65             if (SCK0 & ~pin_SCK) begin
66                 tickShift[2:0] <= { tickShift[1:0], 1'b0 };
67             end
68         end
69         else begin
70             tickShift[2:0] <= ticks[2:0];
71         end
72 
73     end
74 
75 endmodule