It occurred to me that I don’t really have a good way to have a system tick. I tried to fit a counter into the last CPLD. Nothing doing!
So, I think I’ll take the dedicated JTAG programmer and make it also work with the computer. So I need a CS , SCK, Dout, and INT which is Hi-Z or low.
The counter will just be a 12 bit counter that pulls INT low on every bit 10 change. and stop on CS going low. It will be possible to clock out bits 12-11. Super simple. Just a 12 bit counter. A 2 bit shift register, and INT pin control. I should be able to squeeze this into a M4A5 32/32…. Maybe. Just 4 pins.
Of course, this will be a tick of 1.024ms.
I could make the counter count to 1000. But I’d rather just deal with the extra .024.
Though, what would it take to do a 1ms tick? Run the 2MHz signal to a 4 bit counter. The output of the 4th bit will be a 125kHz signal. 125kHz is 125 per ms. So, then a 7 bit counter that resets when it reaches 124 (0x7c). This counter resets once every 1/8ms. So then a 3 bit counter to 1ms. Then a 1 bit counter for 2ms. That last bit is for the fact that many sources might cause an interrupt, so it’s good to have an extra bit so the ISR knows where the count is at.
But, for now, I’ll let this go. I don’t really need a tick quite yet. It’s just nice to know I can get it with 4 lines on one more CPLD.
That CPLD doesn’t have a set of pins for wire wrap. So I’d have to add a header. Or solder one end to the socket. Still lots of options….
BTW, if you don’t know what a system tick is, it’s a way to have the OS know how long it’s been running. It’s useful for such things as IO timeouts, process time slicing, time keeping.
I really should have made the system tick something I thought about early on. It’s pretty important. The fact that I didn’t start to think about it until now is pretty damning. But I did leave enough flexibility in the system. And when I started I did think that CPLDs might be a little more powerful than I’d hoped. Just part of the learning process.