I spent much of last night and this morning getting the Arduino communicating properly with the CPLD. I was able to see the bus control in action, but I wasn’t able to get the address lines working last night. All the CPLD really is is a set of shift registers. How hard can it be?

Finally, I wrote some code that sends back the 5 pin statuses to the C# program in progress responses which can are display while it’s waiting for the final response. Thus I was able to see what the pins are actually doing.

The first thing I did was look at Dout to see if I was shifting out what I was shifting in.

I found a bug in the Verilog with the control register and realized I can’t use it on that particular register:

 1     always @(posedge pin_CLK) begin
 2 
 3         if (pin_nCTRL == `ACTIVELOW) begin
 4 
 5             // clocking in control
 6 //            pin_Dout <= ctrlReg[2]; <-----------------BUG
 7             pin_Dout <= ctrlReg[0];
 8             ctrlReg <= {pin_Din, ctrlReg[2:1]}; 
 9 
10             if (pin_ENABLE == 1'b1) begin
11                 chipReg <= 4'b1111;
12             end
13         end

I’ll keep the bugged CPLD for now since I don’t use the Dout from the control register. I don’t have the same bug in the other shift sections.

Then, I noticed that my address bits weren’t even getting shifted out. Turns out I had my for loop start and end variables reversed. Once that was solved, I was able to see the bits shifting out. And then I saw them on the address lines! Yay!

Next, I looked at the data lines. The first and last seemed to work. I wasn’t sure that the driving was ending properly. But wirewrapping makes it easy to pop a 10K resistor on the board and connect to ground and a data line and Vcc and a data line and write 1 and 0 and make sure that that pulldown/pullup works as expected. And it did!

Here is an example of the flashProg.exe output (address was already programmed):

C:\Users\Mark\Documents\EEProjects\Z80Computer\Tools\Arduino\flashProg\flashProg
\bin\Debug>flashProg.exe wb 5555 80
0: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=0
1: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=0
2: nENABLE=0 nCTRL=0 CLK=1 Din=0 Dout=1
3: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=1
4: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=1
5: nENABLE=0 nCTRL=0 CLK=1 Din=0 Dout=0
6: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=0
7: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=0
8: nENABLE=0 nCTRL=0 CLK=1 Din=0 Dout=0
9: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=0
10: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
11: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
12: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
13: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
14: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
15: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
16: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
17: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
18: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
19: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
20: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
21: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
22: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
23: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
24: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
25: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
26: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
27: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
28: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
29: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
30: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
31: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
32: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=0
33: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=1
34: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
35: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
36: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
37: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=0
38: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=0
39: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=0
40: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
41: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
42: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
43: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
44: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
45: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
46: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
47: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=1
48: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
49: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
50: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=1
51: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
52: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
53: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=1
54: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
55: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
56: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=1
57: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
58: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=1
59: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=1
60: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=1
61: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
62: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
63: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
64: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
65: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
66: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
67: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
68: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
69: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
70: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
71: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
72: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=1
73: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
74: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
75: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=0
76: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=0
77: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
78: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
79: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
80: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
81: nENABLE=0 nCTRL=1 CLK=1 Din=0 Dout=0
82: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
83: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=0
84: nENABLE=0 nCTRL=1 CLK=0 Din=0 Dout=0
85: nENABLE=0 nCTRL=0 CLK=0 Din=0 Dout=0
86: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=0
87: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
88: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
89: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
90: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
91: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
92: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
93: nENABLE=0 nCTRL=0 CLK=1 Din=1 Dout=1
94: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=1
95: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
96: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
97: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=1
98: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
99: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
100: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=1
101: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
102: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=1
103: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=0
104: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=0
105: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=0
106: nENABLE=0 nCTRL=1 CLK=1 Din=1 Dout=0
107: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=0
108: nENABLE=0 nCTRL=0 CLK=0 Din=1 Dout=0
109: nENABLE=0 nCTRL=1 CLK=0 Din=1 Dout=0
Wrote 80 to 5555
>

So, at this point, it looks like the CPLD is working as expected, except for the minor bug.

I’m ready to start wiring up the 39SF020A. I need to write the bulk reading and writing in flashProg.exe.

I should also add a pullup for the ENABLE signal. It has to be high when the Arduino is not connected. That means I need to mount one of the 10K resistor nets with the 8 10K resistors.