The MCU is just a simple bank switcher. I had 4 5 bit banks. The top two bits of the 16 bit address bus: 15 and 14, select a map. Then this map result is used for address bits 17-14.
Originally, I was thinking I would the top bit (essentially A) as the chip select for the SRAM or the flash. But Duh! Ab address line does not a chip select make. So I removed the top address line and added two pin_nCS lines. These will select. And they tristate in reset. Also, the mapping tristates in reset also. This will allow me to use my in-circuit flash programmer. The Arduino will assert RESET to…. I need that needle scratching across the record sound effect… I just realized a problem.
I went to see if the bus control signals tristate on the Z-80 in reset. They don’t. They go high. I DO need to use BUSREQ because they do tri-state in that mode. And I can’t see what happens if I just tie BUSREQ to RESET. Which takes priority? Most likely RESET.
Well, crap! Back to the CPLD design…
[UPDATE: OK, I’ve decided to use 2 switches on the DIP switch instead. So the CPLD pin_nRESET line will connect to the board RESET or CPU BUSREQ line. So all is well with the CPLD…for now.]
Here is the latest MCU code before I realized that I need to use BUSREQ or BUSACK to tristate the bus lines: