I fixed the problem where bus control outputs needed to be tri-stated when the CPLD isn’t enabled. I also made a constraint file. I just had to be careful about which pins go on the CLK/I# pins. Then I assigned them to the A, B, C, and D banks in a logical way. The fitter claims the design fits.
I also got the C# command line program talking with the Arduino. I can send the NOP command. Also read although there is nothing to read. I have programmed the writes that put the flash into byte program mode and erase mode. Also a function that reads and waits for the toggle bits to stop toggling.
I still have a soldering iron in the mail due to arrive at an Amazon Locker near me. So with the verilog, Arduino, and C# code ready to go to test my ability to write flash, I just need the hardware assembled. Pictures will be forthcoming. The plan right now is to populate a JTAG connector and PLCC-44 socket in one corner. I also need the 5V voltage regulator.
I also need to see if I can figure out SVF (Serial Vector Format) files. I want to be able ensure that the CPLD acts the way it is supposed to. SVF test files seems like a way to do that. I can vary and detect the pin voltages on the pins using just JTAG.