OK, so my DigiKey order is scheduled to arrive Monday and I’m gradually solving Verilog timing issues that are new to me even though they must have been issues from time immemorial. I mean, certainly Aristotle and Plato discussed “what do I do when I want to read the data at the rising edge of nWR but then use the data on the rising edge of CLK”. Probably Socrates was back there saying “you young whipper-snappers with your new fangled Verilog.”
But this weekend I’ve got some Shakespeare in the Park to watch. I’ll try to get some verilog written and tested. Starting, I guess with a the flash programmer that will let an Arduino Uno program a flash.