I have questions. I’ve been toying with verilog for a bit now and I have some stuff figured out, but still questions on other stuff.
1) How to deal with reset? Some examples show reset working on an edge. Assuming reset is active low, I could always reset on the posedge. But I can’t change reg’s in more than one always block, so if I use (… or posedge nRESET) how do I know if the always block runs because of the edge of nRESET? I can’t, right? I prefer to use the negedge nRESET, but how can I guarantee that I’d get a falling edge at power up?
2) How to use the posedge of nWR to write a register from the the CPU?
I may add more later….