So, the Z-80 is an old CPU. My first computer was a TRS-80 which had a 2MHz Z-80 with 48k of RAM. There was no disk drive. Instead you used a tape recorder. You pushed the Record and Play buttons down, then typed something into the command prompt that sent out your program as sound. If you wanted to reload, you’d enter some command to make it start listening, then replay the tape.

Of course, that has nothing to with CPLDs. What is does have to do with, is the Z-80 is really really old and requires lots of glue logic. Back in the day that was done with 74LSxx chips that had four or so single logic gates. And that’s a lot of surface area for single logic gates.

These days, we can use CPLDs. Sort of.

The Z-80 is a 5V processor and while there is still some 5V stuff out there–including some Arduinos, 5V is the voltage of people who like ABBA. And I love ABBA! Hey, I was born in 1968, what can I say?

Anyway, I don’t want to deal with all those logic chips, so CPLDs are the way to go. A CPLD is a “complex programmable logic device”. It is a chip that is programmable to act as if it were a whole pile of logic chips.

You can program it with VHDL or with Verilog. VHDL is reminiscent of FORTRAN, while Verilog is reminiscent of C. As a C programmer, Verilog is annoying because { and } are replaced by begin and end and then { and } are used to concatenate bit arrays.

If you want to use Verilog, it’s not super hard to learn. You need to learn where the semocolons go. the difference between “input A [3:0]” and “input [3:0] A”, and always and assign. You need to learn the difference between wire and reg, how to work a bidirectional pin (hint: write 1’bz to tristate it). You need to keep an eye on synthesizability.

What is synthesizability? Ah, I’m glad you asked! It is the ability of a verilog program to be converted into a netlist that can be loaded into a CPLD. Just because you can write a verilog description, it doesn’t mean it can be converted into a meaningful netlist. Just as it’s easy to write a program that finds all chess moves–you just can find a computer that will run it to completion.

You also need to write a testbench to ensure that you logic works as expected. The nice thing about testbenches is that they don’t have to be synthesizable.

Anyway, I decided for reason in particular to use the Lattice brand CPLDs.. There is Xilinx and Alterra as well, but there are some Lattice PLCC-44 5V CPLDs and their older software is free, so I went with them.

At $5 a chip, it’s a very reasonable chip. Of course, if you’re wirewrapping, you’ll need a 44 lead PLCC  socket and 44 pins of  wirewrapping goodness for which I’m using headers.

What does PLCC mean? Well, it’s a type of packaging. The chip is encased in plastic or ceramic and have 44 conductiv e leads coming out that go down and bend under the chip in a sort of J. You can solder them to pads down below. Or pop it into a socket which connects with the side of the J. So they are pretty versatile. There is a company in the UK that sells wire wrap PLCC-44 sockets, but I’m using Digikey and they don’t have them. So I’ll deal with it.

The sockets are a buck, 4 2x6 headers a a couple bucks for all 4. And you’ll want a 2x5 socket for the JTAG connections.

If this post raised more questions than answers, worry not. I intend to get around to a ton of this stuff later.